
`ifdef FLIPFLOP
`else
`include "flipflop.v"
`define FLIPFLOP
`endif

`ifdef DECODER
`else
`include "decoder.v"
`define DECODER
`endif

`ifdef COMPARER
`else
`include "comparer.v"
`define COMPARER
`endif

`ifdef ENCODER
`else
`define ENCODER
`include "encoder.v"
`endif

`ifdef MULTIPLEXOR
`else
`define MULTIPLEXOR
`include "multiplexor.v"
`endif

module tlb(virtualSelect,fisicaIn, virtualIn, protIn, index, write, reset, clock, hit, fisicaOut, protOut);
        input[4:0] fisicaIn;
        input[5:0] virtualIn,virtualSelect;
        input[2:0] protIn;
        input[2:0] index;
        input write, reset, clock;
 
        output hit;
        output[4:0] fisicaOut;
        output[2:0] protOut;


	//initial
	//begin
	//$dumpfile( "test.vcd" );
	//$dumpvars( 1, tlb );
	//end

	wire [5:0] wflipFlopVirtualOut0;
	wire [5:0] wflipFlopVirtualOut1;
	wire [5:0] wflipFlopVirtualOut2;
	wire [5:0] wflipFlopVirtualOut3;
	wire [5:0] wflipFlopVirtualOut4;
	wire [5:0] wflipFlopVirtualOut5;
	wire [5:0] wflipFlopVirtualOut6;
	wire [5:0] wflipFlopVirtualOut7;
	
	wire [4:0] wflipFlopFisicaOut0;
	wire [4:0] wflipFlopFisicaOut1;
	wire [4:0] wflipFlopFisicaOut2;
	wire [4:0] wflipFlopFisicaOut3;
	wire [4:0] wflipFlopFisicaOut4;
	wire [4:0] wflipFlopFisicaOut5;
	wire [4:0] wflipFlopFisicaOut6;
	wire [4:0] wflipFlopFisicaOut7;

	wire [2:0] wflipFlopProtOut0;
	wire [2:0] wflipFlopProtOut1;
	wire [2:0] wflipFlopProtOut2;
	wire [2:0] wflipFlopProtOut3;
	wire [2:0] wflipFlopProtOut4;
	wire [2:0] wflipFlopProtOut5;
	wire [2:0] wflipFlopProtOut6;
	wire [2:0] wflipFlopProtOut7;
	
	wire wAndWeIndxOut0;
	wire wAndWeIndxOut1;
	wire wAndWeIndxOut2;
	wire wAndWeIndxOut3;
	wire wAndWeIndxOut4;
	wire wAndWeIndxOut5;
	wire wAndWeIndxOut6;
	wire wAndWeIndxOut7;

	wire wAndRstCmpOut0;
	wire wAndRstCmpOut1;
	wire wAndRstCmpOut2;
	wire wAndRstCmpOut3;
	wire wAndRstCmpOut4;
	wire wAndRstCmpOut5;
	wire wAndRstCmpOut6;
	wire wAndRstCmpOut7;
	


	wire wRstOut0;
	wire wRstOut1;
	wire wRstOut2;
	wire wRstOut3;
	wire wRstOut4;
	wire wRstOut5;
	wire wRstOut6;
	wire wRstOut7;

	wire wCmpOut0;
	wire wCmpOut1;
	wire wCmpOut2;
	wire wCmpOut3;
	wire wCmpOut4;
	wire wCmpOut5;
	wire wCmpOut6;
	wire wCmpOut7;
	
	

	wire [7:0] wDecoder;
	wire [2:0] wEncoder;	
	
	wire [15:0] wNullOut16;
	wire [1:0] wNullOut2;
	wire [1:0] wNullIn2;
	wire wNullOut1;

	
	Decoder3x8 decoder(index,wDecoder);		 
	
	and andWeIndx0(wAndWeIndxOut0,write,wDecoder[0]);
	and andWeIndx1(wAndWeIndxOut1,write,wDecoder[1]);
	and andWeIndx2(wAndWeIndxOut2,write,wDecoder[2]);
	and andWeIndx3(wAndWeIndxOut3,write,wDecoder[3]);
	and andWeIndx4(wAndWeIndxOut4,write,wDecoder[4]);
	and andWeIndx5(wAndWeIndxOut5,write,wDecoder[5]);
	and andWeIndx6(wAndWeIndxOut6,write,wDecoder[6]);
	and andWeIndx7(wAndWeIndxOut7,write,wDecoder[7]);
	


	
	Flip_flop_reset_enable14 FF0(clock,{wflipFlopVirtualOut0,wflipFlopFisicaOut0,wflipFlopProtOut0},{virtualIn,fisicaIn,protIn},wAndWeIndxOut0,reset);

	Flip_flop_reset_enable14 FF1(clock,{wflipFlopVirtualOut1,wflipFlopFisicaOut1,wflipFlopProtOut1},{virtualIn,fisicaIn,protIn},wAndWeIndxOut1,reset);	
	 
	Flip_flop_reset_enable14 FF2(clock,{wflipFlopVirtualOut2,wflipFlopFisicaOut2,wflipFlopProtOut2},{virtualIn,fisicaIn,protIn},wAndWeIndxOut2,reset);	
	 
	Flip_flop_reset_enable14 FF3(clock,{wflipFlopVirtualOut3,wflipFlopFisicaOut3,wflipFlopProtOut3},{virtualIn,fisicaIn,protIn},wAndWeIndxOut3,reset);	
	 
	Flip_flop_reset_enable14 FF4(clock,{wflipFlopVirtualOut4,wflipFlopFisicaOut4,wflipFlopProtOut4},{virtualIn,fisicaIn,protIn},wAndWeIndxOut4,reset);	
	 
	Flip_flop_reset_enable14 FF5(clock,{wflipFlopVirtualOut5,wflipFlopFisicaOut5,wflipFlopProtOut5},{virtualIn,fisicaIn,protIn},wAndWeIndxOut5,reset);	
	 
	Flip_flop_reset_enable14 FF6(clock,{wflipFlopVirtualOut6,wflipFlopFisicaOut6,wflipFlopProtOut6},{virtualIn,fisicaIn,protIn},wAndWeIndxOut6,reset);	

	Flip_flop_reset_enable14 FF7(clock,{wflipFlopVirtualOut7,wflipFlopFisicaOut7,wflipFlopProtOut7},{virtualIn,fisicaIn,protIn},wAndWeIndxOut7,reset);	
	 
	Biestable_reset_enable R0(clock,reset,wRstOut0,1,wAndWeIndxOut0);
	Biestable_reset_enable R1(clock,reset,wRstOut1,1,wAndWeIndxOut1);
	Biestable_reset_enable R2(clock,reset,wRstOut2,1,wAndWeIndxOut2);
	Biestable_reset_enable R3(clock,reset,wRstOut3,1,wAndWeIndxOut3);
	Biestable_reset_enable R4(clock,reset,wRstOut4,1,wAndWeIndxOut4);
	Biestable_reset_enable R5(clock,reset,wRstOut5,1,wAndWeIndxOut5);
	Biestable_reset_enable R6(clock,reset,wRstOut6,1,wAndWeIndxOut6);
	Biestable_reset_enable R7(clock,reset,wRstOut7,1,wAndWeIndxOut7);

	Comparer6x1 C0(virtualSelect,wflipFlopVirtualOut0,wCmpOut0);
	Comparer6x1 C1(virtualSelect,wflipFlopVirtualOut1,wCmpOut1);
	Comparer6x1 C2(virtualSelect,wflipFlopVirtualOut2,wCmpOut2);
	Comparer6x1 C3(virtualSelect,wflipFlopVirtualOut3,wCmpOut3);
	Comparer6x1 C4(virtualSelect,wflipFlopVirtualOut4,wCmpOut4);
	Comparer6x1 C5(virtualSelect,wflipFlopVirtualOut5,wCmpOut5);
	Comparer6x1 C6(virtualSelect,wflipFlopVirtualOut6,wCmpOut6);
	Comparer6x1 C7(virtualSelect,wflipFlopVirtualOut7,wCmpOut7);

	and andRstCmp0(wAndRstCmpOut0,wRstOut0,wCmpOut0);
	and andRstCmp1(wAndRstCmpOut1,wRstOut1,wCmpOut1);
	and andRstCmp2(wAndRstCmpOut2,wRstOut2,wCmpOut2);
	and andRstCmp3(wAndRstCmpOut3,wRstOut3,wCmpOut3);
	and andRstCmp4(wAndRstCmpOut4,wRstOut4,wCmpOut4);
	and andRstCmp5(wAndRstCmpOut5,wRstOut5,wCmpOut5);
	and andRstCmp6(wAndRstCmpOut6,wRstOut6,wCmpOut6);
	and andRstCmp7(wAndRstCmpOut7,wRstOut7,wCmpOut7);

	Encoder8x3 Encoder({wAndRstCmpOut7,wAndRstCmpOut6,wAndRstCmpOut5,wAndRstCmpOut4,wAndRstCmpOut3,wAndRstCmpOut2,wAndRstCmpOut1,wAndRstCmpOut0},wEncoder);
	
	Multiplexor8x1 Multiplexor({wflipFlopFisicaOut0,wflipFlopProtOut0},{wflipFlopFisicaOut1,wflipFlopProtOut1},{wflipFlopFisicaOut2,wflipFlopProtOut2},{wflipFlopFisicaOut3,wflipFlopProtOut3},{wflipFlopFisicaOut4,wflipFlopProtOut4},{wflipFlopFisicaOut5,wflipFlopProtOut5},{wflipFlopFisicaOut6,wflipFlopProtOut6},{wflipFlopFisicaOut7,wflipFlopProtOut7},{fisicaOut,protOut},wEncoder);

	or orhit(hit,wAndRstCmpOut0,wAndRstCmpOut1,wAndRstCmpOut2,wAndRstCmpOut3,wAndRstCmpOut4,wAndRstCmpOut5,wAndRstCmpOut6,wAndRstCmpOut7);	   
	
	/*
	reg hit;
	reg [4:0] fisicaOut;
	always @ (posedge clock)
		begin
			hit = 1;
			fisicaOut = 0;
		end		*/
		
endmodule

